Register Transfer Level


Register Transfer Level

Das Register Transfer Level (RTL, deutsch: Registertransferebene) ist eine Abstraktionsebene in der Hardware-Modellierung von digitalen Schaltkreisen. Beim Entwurf auf dieser Ebene wird das System durch den Signalfluss zwischen den Registern spezifiziert.

Das RTL wird in Hardwarebeschreibungssprachen wie VHDL und Verilog verwendet, um High-level-Darstellungen von Schaltkreisen zu erzeugen. Von diesen lassen sich Darstellungen auf niedrigeren Ebenen und schließlich die konkrete Hardware synthetisieren.

Mit Software-Tools lässt sich die RTL-Beschreibung in eine Netzliste übersetzen, aus der schließlich durch Placement und Routing ein physikalisches Layout erzeugt wird.

Die Synthese, die eine logische Schaltung aus einem RTL-Modell generiert, nennt man RTL-Synthese.

Literatur

  • Peter Marwedel: Embedded System Design. Springer, Dordrecht 2006, S. 81, ISBN 0-387-29237-3.

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